Our laboratory focuses on materials design and process development for advanced semiconductor packaging, aiming to address warpage, thermal stress, and interfacial reliability issues caused by coefficient of thermal expansion mismatch within packaging structures. In terms of materials design, we develop zirconium vanadate (ZrV₂O₇)-based negative thermal expansion materials. Through doping modification and composite filler design, these materials are incorporated into epoxy-based underfill systems to reduce the overall coefficient of thermal expansion and enhance dimensional stability and reliability. In terms of processing technologies, we develop silicon substrate surface activation, electroless copper plating, and electroplating thickening processes for the fabrication of uniform copper films, conductive layers, and high-thermal-conductivity interfacial materials. These approaches aim to improve electrical conductivity, thermal management, and interfacial bonding performance in semiconductor packaging.